Input/Output Organization

INPUT/ outfit ORGANIZATION cominging I/O twirls I/O port wine Input/ issue mechanism retentivity-mapped I/O y pp / Programmed I/O stays Direct repositing Access B practices Synchronous good deal a synchronized Bus I/O in CO and O/S Programmed I/O fails DMA (Direct remembering Access) A batch is a shargond communicating link, which uses angiotensin-converting enzyme , rotary of wires to connect multiple sub trunks. The cardinal study advantages of the muckle organization atomic physical body 18 versatility and disordered bell. Accessing I/O catchs intimately roomrn computing machines use hit passenger car arrangement for connecting I/O plaits to mainframe computer & Memory The handler enables solely the inventions committed to it to exchange selective tuition Bus lies of 3 set of linages Address, information, fit mainframe places a lift officular shell out ( queer for an I/O Dev. ) on administer inceptions Device which recognizes t his extend responds to the see to its issued on the mark off paths mainframe collects for each memorialise / Write The information leave be placed on info patronages hardw atomic play 18 to connect I/O impostures to b t mass port Circuit Address De encipherr Control Circuits Data ushers stance regis establishs The Registers in I/O Interface pi voltaic pile and condition Flags in Status Registers like ug heapiness organisationss, SOUT Registers, SIN Data Registers, like Data-IN, Data-OUT I/O substance abuser interface for an arousal craft Memory Address central mainframe Data Control Address Add De economyrs Control C t l roofys Data d t t D t and lieu storys I/O /O Interface Input wile (s) p ( ) Input getup mechanism h i Memory mapped I/O Programmed I/O hampers DMA (Direct retrospection Access)A deal topology generally hold ups a set of deem direct contrasts and a set of information lines. The escort lines argon employ to aim indicates and ack right a substanceledgments, and to prefigure what grammatical face of information is on the driveive information lines. The catch lines atomic number 18 apply to destine what the passel contains and to implement the sightbar topology protocol. The selective information lines of the bus give birth information mingled with the source and the destination. This information whitethorn consist of selective information, complex commands, or utteres. Buses are traditionally classified as mainframe computer- retrospect di i ll l ifi d buses or I/O buses or modified purposed buses (Graphics, etc. ). mainframe computer reminiscence buses are short, generally tall gear locomote, and matched to the memory system so as to maximize memorycentral bear oning unit bandwidth. I/O b buses, b contrast, fundament be lengthy, can pass many by t t b l th h types of twistings affiliated to them, and often bedevil a considerable range in the selective inform ation bandwidth of the pulls connected to them. I/O buses do non typically interface like a shot to the memory simply use either a mainframe computer-memory or a backplane bus to connect to memory. The major disadvantage of a bus is that it creates a communication obstruct possibly limiting the maximum I/O bottleneck, byput.When I/O essential pass through a single bus, the bus bandwidth of that bus limits the maximum I/O throughput. Reason why b R h bus d i design is so serious i diffi lt the maximum bus speed is largely limited by physiologic factors the length of the bus and the number of crafts. These physical limits pr up to nowt us from playactning the bus arbitrarily debauched. In addition, the need to tide all oer a range of gizmos with widely varying latencies and entropy deepen casts overly makes bus design challenging. it becomes difficult to run many parallel wires at juicy speed due to clock reorient and reflection reflection.The two basic s hunnings for communication on the bus are synchronous and asynchronous. If a bus is synchronous (e. g. central central processing unit-memory), it includes a clock in the chair lines and a fixed protocol for communicating that is sexual intercourse to the clock. g This type of protocol can be implemented easily in a small finite kingdom machine. Because the protocol is pre regularized and involves little logic, the bus can run very fast and the interface logic testament be small. Synchronous buses have two major disadvantages First, every thingmajig on the bus must run at the similar clock rate. Second, because of clock skew problems, synchronous buses can non be long if they are fast. An A asynchronous b h bus i non clocked. It can gruntle a is t l k d d t wide variety of spins, and the bus can be lengthened without worrying about clock skew or synchronization problems. To arrange the contagion of info mingled with directer and receiver, an asynchronous bus uses a shake protocol. Three surplus defend lines required for hand-shaking ReadReq utilize to pick up a carry pray for memory. The distrisolelye is put on the information lines at the equivalent beat.DataRdy Used t i di t th t th d t D t Rd U d to indicate that the data word is now ready on the di d th data lines asserted by Output/Memory and Input/I_O Device. Ack Used to recognize the ReadReq or the DataRdy house of the parvenue(prenominal) party. I/O Dev. Memory Steps aft(prenominal) the cunning signals a bespeak by raising ReadReq and putting the lot on the Data lines 1. When memory sees the ReadReq line, it reads the address from the data bus and raises Ack to indicate it has been seen. 2. As the Ack line is uplifted I/O releases the ReadReq and data lines. g / q 3.Memory sees that ReadReq is beginning and drops the Ack line to experience the ReadReq signal (Mem. Reading in advancement now). 4. This step starts when the memory has the data ready. It places t he data from the read pass on on the data lines and raises DataRdy. 5. The I/O whatsis sees DataRdy, reads the data from the bus, and signals that it has the data by raising Ack. 6. On the Ack signal, M/M drops DataRdy, and releases the data lines. 7. Finally, the I/O twirl, seeing DataRdy go low, drops the Ack line, which indicates that the transmission is accomplished. Memory mapped I/O I/O stratagems and the memory share the said(prenominal) address spot the property, arrangement is called Memory-mapped I/O. In Memory-mapped I/O portions of address space are assigned to I/O wrenchs and reads and writes to those addresses are interpreted as commands to the I/O device. DATAIN is the address of the input buffer associated with the keyboard. Move DATAIN, R0 reads the data from DATAIN and stores them into mainframe computer read R0 Move R0, DATAOUT propels the limit of register R0 to side DATAOUT g Option of special I/O address space or incorporate as a part of memor y address space (address bus is same al steerings).When the central processor places the address and data on the memory bus, the memory system ignores the movement because the address indicates a portion of the memory space utilise for I/O. The device comptroller, however, sees the accomplishment, records the data, and transmits it to the device as a command. User weapons platforms are p p g prevented from issuing I/O g / works today because the OS does not provide adit to the address space assigned to the I/O devices and thus the addresses are protected by the address translation. Memory mapped I/O can also be used to transmit data by writing or reading to select addresses.The device uses the address to determine the type of command, and the data may be provided by a write or obtained by a read. A program pick up usually requires several separate I/O exertions. Further more than, the processor may have to interrogate the lieu of the device between individual commands t o determine whether the command effected success risey. DATAIN DATAOUT STATUS CONTROL 7 6 5 4 DIRQ KIRQ DEN mickle SOUT SIN 3 2 1 0 I/O operation involving keyboard and display devices Registers DATAIN, DATAOUT, STATUS, CONTROL Flags SIN, SOUT Provides perspective information for keyboard nd display unit KIRQ, DIRQ Keyboard, pompousness amputate demand bits DEN, KEN Keyboard, screening Enable bits Programmed I/O central affect unit has direct control over I/O S Sensing place i t t Read/write commands Transferring data CPU waits for I/O module to complete operation Wastes CPU time In this case, use utilise I/O focal point manual in the processor. These I/O operate operating instructions can declare both the device number and the command word (or the location of the command word in memory). The processor perishs the device address via a set of wires popularly included as part of the I/O bus.The actual command can be transmitted over the data lines in the bus. b us (example Intel IA-32) IA-32). By making the I/O instructions illegal to execute when not in kernel or supervisor elbow room user programs can be mode, prevented from accessing the devices at once. The process of headically checking post bits to see if it is time for the next I/O operation, is called polling. Polling is the easyst way for an I/O device to bring with the processor processor. The I/O device simply puts the information in a Status register, register and the processor must come and get the information.The processor is completely in control and does all the work. A ISA program to read one line from the keyboard, store it in memory buffer and echo it back to the display buffer, The disadvantage of polling is that it can waste a lot of processor time because processors are so more than faster than I/O devices devices. The processor may read the Status register many times, wholly to buzz off that the device has not yet stainless a comparatively slow I/O operat ion, or that the mouse has not budged since the last time it was polled.When the device completes an operation, we must s bowl read the status to determine whether it (I/O) was successful. Overhead in a polling interface travel by to the invention of frustrates to give the sack the processor when an I/O device requires worry from the processor. get around-driven I/O, snap off driven I/O employs I/O bring outs to indicate to the processor that an I/O device needs attention. When a device wants to notify the processor that it has finish some operation or needs attention, it causes the processor to be crashed.Interrupts I/O die mainframe When I/O Device is ready, it sends the INTERRUPT signal to processor via a dedicated control line Using ruin we are ideally eliminating WAIT period In solvent to the pick, the processor executes the Interrupt Service Routine (ISR) on the whole the registers flags program tallyer values are protected registers, flags, by the process or earlier footrace ISR The time required to save status & restore contrisolelye to instruction execution operating cost ? Interrupt Latency p y nterrupt-acknowledge signal I/O device interface p y accomplishes this by execution of an instruction in the frustrate-service flake (ISR) that accesses a status or data register in the device interface implicitly informs the device that its interrupt request has been recognized. IRQ signal is then removed by device. ISR is a sub-routine may belong to a diametrical user than the one macrocosm executed and then halted. The condition enter flags and the contents of any registers used by both the interrupted program and the interrupt-service interrupt service routine are relieve and restored restored.The concept of interrupts is used in operating systems and i many control applications, where processing of d in l li i h i f certain routines must be accurately timed relative to external events (e. g. real time processing). Interrup t Hardware p rob up Pull-up resister INTR = INTR1 +.. +INTR n INTR An equivalent electric circuit for an open drainpipe bus used to implement a open-drain ballpark interrupt-request line Interrupt Hardware Supply pp y R INTR Processor Pull-up resister INTR 1 INTR 2 INTR 3 INTR = INTR1 +.. +INTR n GND INTR Enabling and disable Interrupts Device activates interrupt signal line and waits with this signal activated until processors attends The interrupt signal line is active during execution of ISR and till the device caused interrupt is serviced Necessary to tell that the active signal does not lead to successive abatements (level-triggered input) ca utilize (level triggered the system to diminution in infinite loop. What if the same d i h h device i interrupts again, within an ISR ? i i hi Three methods of Controlling Interrupts (single device) Ignoring interrupt Disabling interrupts Special Interrupt request line Ignoring Interrupts Processor hardware ignores the inter rupt request line until the execution of the number one instruction of the ISR completed Using an interrupt disable instruction after the premiere signal instruction of the ISR no further interrupts A return from interrupt instruction is completed before further interruptions can give-up the g force Disabling Interrupts Processor automatically disables interrupts before starting the execution of the ISR The processor saves the contents of PC and PS (status register) before playing interrupt modify. The interrupt-enable is set to 0 no further interrupts allowed When return from interrupt instruction is executed the contents of the PS are restored from the stack, and the interrupt enable is set to 1 Special Interrupt line p p Special interrupt request line for which the interrupt treatment circuit responds tho t th l di h dli i it d l to the leading edge of d f the signal Edge triggered g gg Processor receives totally one request disregarding of how long the line is activated N separate i t No t interrupt di bli t disabling i t instructions charge sequence of events involved in handling an interrupt request from a single device. Assuming that interrupts are enabled, the hobby is a typical scenario 1. 1 The device raises an interrupt request request. 2. The processor interrupts the program soon being executed. t d 3. Interrupts are disabled by changing the control bits in the PS (except in the case of edge-triggered interrupts) interrupts). 4. The device is informed that its request has been recognized, and in response, it deactivates the interrupti d di d ti t th i t t request signal. . The action requested by the interrupt is performed by the interrupt-service routine. 6. Interrupts are enabled and execution of the interrupted program is resumed. Handling treble Devices Multiple devices can initiate interrupts p p They uses the common interrupt request line y p q Techniques are q Polling Vectored Interrupts p Interrupt Nesting Daisy Chaining y g Polling Scheme The IRQ (interrupt request) bit in the status register is set when a device is requesting an interrupt. The Interrupt service routine poll the I/O devices connected to the bus. The world-class device coming togethered with the IRQ bit set is serviced and the office is invoked. Easy to implement, but too much time spent on checking the IRQ bits of all devices, though some devices may not be requesting service. Vectored Interrupts Device requesting an interrupt identifies itself today to the processor The device sends a special code to the processor over the bus. The code contains the identification of the device device, starting address for the ISR, address of the branch to the ISR PC finds the ISR address from the code. To add flexibility for multiple devices comparable ISR is executed by the processor utilize a branch address to the suppress routine device specified Interrupt Vector. An interrupt vector is the memory address of an interrupt handler, or an index into an ramble called an interrupt vector slacken or dispatch slacken a table of interrupt vectors (pointers to routines that handle interrupts).Interrupt vector tables contain the memory addresses of interrupt handlers. When an interrupt is generated, the processor saves its execution state via a stage setting switch, and begins execution of the interrupt handler at the interrupt b i ti f th i t t h dl t th i t t vector. The Interrupt Descriptor Table ( p p (IDT) is particular to the ) p I386 architecture. It tells where the Interrupt Service Routines (ISR) are located. from each one interrupt number is reserved for a specific purpose. For example, 16 of the vectors are reserved for the 16 IRQ lines.Q On PCs, the interrupt vector table (IVT or IDT) consists of 256 4-byte pointers the first 32 (0-31 or 00-1F) of which are reserved f for processor exceptions the rest f for hardware interrupts, software product interrupts. This resides in the fi rst 1 K of addressable memory. Interrupt Nesting Pre-Emption of low antecedence Interrupt by other high Pre Emption priority interrupt is know as Interrupt nesting. Di bli Disabling I t Interrupts d i t during th execution of th ISR the ti f the may not opt devices which need immediate attention. Need a priority of IRQ devices and accepting IRQ from a high priority device. The priority level of the processor can be changed y y dynamically. The privileged instruction write in the PS (processor status word) that encodes the processors priority word), priority. Interrupt Nesting (contd. ) Pro ocessor INTR1 Device 1 INTA 1 Device 2 INTRp .. . Device p INTA p anteriority arbitration circuit Organizing I/O devices in a prioritized construction. g g / p Each of the interrupt-request lines is assigned a different priority level level. The processor is interrupted only by a high priority device. Daisy Chaining The interrupt request line INTR is common to all the devices The i nterrupt acknowledgement line INTA is connected to devices in a DAISY ambit way INTA propagates consecutively through the devices Device that is electrically closest to the processor gets high hi h priority i i Low priority device may have a danger of STARVATION INTR P Processor r Device D i 1 INTA Device D i 2 .. Device n D i Daisy Chaining with Priority Group Combining Daisy set uping and Interrupt nesting to form p priority multitude yg p Each base has different priority levels and within each group devices are connected in daisy orbit wayINTR1 Proc cessor Device 1 Device 1 INTA 1 INTR p . . . . Device D i 1 INTA p Priority arbitration circuit Device D i 1 Arrangement of priority groups Direct Memory Access (DMA) For I/O transportation, Processor determines the status of I/O devices, by Polling Waiting for Interrupt signal Considerable overhead is incurred in above I/O canalize processing To tilt large blocks of data at high Speed, between orthogonal devices & M ain Memory, DMA approach is often used DMA dominance allows data manoeuver directly between I/O device d i and d Memory, M with i h minimal i l intervention i i of f processor. Direct Memory Access (DMA) DMA controller acts as a Processor, but it is controlled by CPU To initiate transfer of a block of words, the processor sends the following data to controller The starting address of the memory block The word count h d Control to specify the mode of transfer such(prenominal) as read or write A control to start the DMA transfer DMA controller performs the requested I/O operation and sends a interrupt to the processor upon effect 1 Status and Control beginning address Word count In ? ? ? IRQ 30 IE 1 R/W 0 Done DMA interface g g First register stores the starting address Second register stores Word count Third register contains status and control flags Bits and Flags R/W Done IRQ IE 1 order Data transfer finishes Interrupt request Raise interrupt (enable) after Data Transf er 0 WRITE Processor Main memory disk/DMA controller DMA controller Printer Keyboard Disk Disk Network Interface Use of DMA ascendance in a computer system Memory accesses by the processor and DMA ascendence are interwoven DMA devices have higher(prenominal) priority then processor over BUS control rhythm method of birth control larceny- DMA Controller steals memory cycles from processor, though processor originates most(prenominal) memory access. Block or Burst mode- The of data without interruption Conflicts in DMA Processor and DMA, Two DMA controllers, try to use the Bus at the same time to access the main memory DMA controller may given exclusive access to the main memory to transfer a blockDMA and Interrupt Breakpoints During D i an I t Instruction Cycle ti C l Bus Arbitration Bus hold in device that initiates data transfers on the bus. The next device can wages control of the bus after the current quash relinquishes control Bus Arbitration process by which the next device to become master is selected Centralized and Distributed Arbitration BBSY P Processor r BR BG1 DMA controller 1 BG2 DMA controller 2 A simple arrangement for bus arbitration using a daisy chain BR (bus request ) line open drain line the signal on this line is a logical OR of the bus request from all the g q DMA devices BG (bus grant) line processor activates this line indicating (acknowledging) to all the DMA devices (connected in daisy chain fashion) that the BUS may be used when its free free. BBSY (bus busy) line open collector line the current bus master i di b indicates d i devices that i i currently using h it is l i the bus by signaling this line BBSY Processor BR BG1 DMA controller 1 BG2DMA controller 2 Sequence of signals during data transfer of bus mastership Centralized Arbitration smash unit (bus arbitration circuitry) connected to the bus Processor is normally the bus master, unless it grants bus mastership to DMA For the timing/control, in previous sheer DMA controller 2 requests and acquires bus mastership and after releases the bus. During its tenure as the bus master, it may perform one or more data transfer operations, depending on whether it is p , p g operating in the cycle stealing or block mode.After it releases the bus, the processor resumes bus mastership. Distributed Arbitration alone devices waiting to use the bus has to carry out the arbitration process no central arbiter Each device on the bus is assigned with a identification number 4-bit One or more devices request the bus by asserting q y g the start-arbitration signal and place their identification number on the four open collector lines ARB0 through ARB3 are the four open collector lines One among the four is selected using the code on the lines and one with the highest ID numberA distributed arbitration scheme Assume that two devices, A and B, having ID numbers game 5 and 6, respectively, are requesting the use of the bus. Device A transm its the warning 0101, and device B transmits the practice 0110. p The code seen by both devices is 0111. Each device compares the pattern on the arbitration lines to its own ID, starting from the most significant bit. If it detects a dissimilitude at any bit position, it disables its drivers at that bit position and for all lower-order bits. It does so by placing a 0 at the input of these drivers drivers.In the case of our example, device A detects a difference on line ARB I. Hence, it disables its drivers on diff li I H i di bl i d i lines ARB 1 and ARBO. This causes the pattern on the arbitration lines to change to 0110, which kernel that B has won the contention. Universal incidental Bus (USB) The USB supports two speeds of operation called lowoperation, low speed (1. 5 megabits/s) and full-speed (12 megabits/s). The Th most recent revision of the bus stipulation (USB i i f h b ifi i 2. 0) introduced a tercet speed of operation, called high-speed (480 megabits/s).The USB ha s been designed to jibe several key objectives -P Provide a simple, low-cost, and easy to use interconnection id i l l t d t i t ti system that overcomes the difficulties due to the limited number of I/O ports available on a computer Accommodate a wide range of data transfer characteristics for I/O devices, including telephone and meshwork connections / , g p Enhance user convenience through a plug-and-play mode of operation USB Bandwidths A low-speed rate of 1. 5 Mbit/s (183 kB/s) is defined by USB 1. 0.It is intended primarily to save cost in lowbandwidth human interface devices (HID) such as keyboards, ( ) y , mice, and joysticks. The full-speed rate of 12 Mbit/s (1. 43 MB/s) is the full speed ( 1. 43 basic USB data rate defined by USB 1. 1. All USB hubs support full-bandwidth. A high-speed (USB 2. 0) rate of 480 Mbit/s (57 MB/s) was introduced in 2001. All hi-speed devices are capable of go back to full bandwidth operation if required they are full-bandwidth backward compa tible. Connectors are identical. SuperSpeed ( d (USB 3. 0) rate produces upto 4800 Mbit/s ) d bi / (572 MB/s or 5 Gbps)Each node of the tree has a device called a hub, which acts as an intermediate control point between the array and the I/0 devices devices. At the root of the tree, a root hub connects the entire tree to the entertain computer. The leaves of the tree are the I/0 p / devices being served. The tree structure enables many devices to be connected eon using only simple point-topoint serial links. Each hub has a number of ports where devices may be connected, including other hubs. In normal operation, a hub g copies a subject matter that it receives from its upstream connection to all its downstream ports.As A a result, a mental object sent b the soldiery computer is lt t by th h t t i circularize to all I/O devices, but only the addressed device will respond to that message. A message from an I/O device is sent only upstream towards the root of the tree and is no t seen by other devices. Hence, th USB enables th h t t communicate with the I/O H the bl the host to i t ith th devices, but it does not enable these devices to communicate with each other. The USB operates strictly on the basis of polling. A device may send a message only in response to a poll message from the host host.Hence, upstream messages do not encounter conflicts or interfere with each other, as no two devices can send other messages at the same time. This limitation allows hubs to be simple, low-cost devices. USB protocol requires that a message transmitted on a highspeed link is always transmitted p y at high speed, even when the ultimate receiver is a low-speed device. device Hence, a message intended for device D is sent at high speed from the root hub to hub A, then A forwarded at low speed to device D. The latter transfer will take a long time, during which highl ti d i hi h hi h speed traffic to other nodes is allowed to continue.Each device on the USB, whether it is a hub or an I/O device, is assigned a 7-bit address. This address is local to the USB tree and is not related in any way to the addresses used on the processor bus. A hub may have any number of devices or other hubs connected to it, and addresses are assigned arbitrarily. When a device is first connected to a hub, or when it is power on, it has the address 0. The hardware of the hub to which this device is connected is capable of detecting that the device has been connected, and it records this f d hi fact as part of i own status i f f its information. Periodically, the host polls each hub to collect status information and learn about new devices that may have been added or disconnected. When the host is informed that a new device has been connected, connected it uses a sequence of commands to send a reset signal on the corresponding hub port, read information from the device about its capabilities, send configuration information to the device, and assign the device a unique USB address. O d i d i th d i i dd Once this thi sequence is completed the device begins normal operation and responds only to the new address. Read about USB protocols isochronous traffic on USB and USB FRAME